1. Field of the Invention
The present invention relates generally to a transmitting and receiving circuit, a mobile communication terminal device employing the same and a control method therefor. More particularly, the invention relates to an improvement of generation method of spread or despread code in a transmitting and receiving circuit of a CDMA (Code Division Multi Access) type mobile communication terminal device.
2. Description of the Related Art
In a transmitting and receiving portion of a CDMA system, codes are generated for spreading and despreading required for processing a transmission and reception data. Typically, these codes are chip rate signals having certain constant periods. In the conventional system, when physical channels (kind of channel, code number and so forth) to be transmitted and received to and from the transmitting and receiving portion are assigned, code generators of shift register construction are constantly operated to continuously output codes necessary for transmission and reception.
In such system, upon performing discontinuous transmitting and receiving operation, such as a TDD (Time Division Duplex) mode, a DTX control (Discontinuous Transmission) control, a packet transmission and so forth, in CDMA system, for example, the code generators have to continue operation even in a time zone where transmission and reception are not performed to waste extra current.
Therefore, a technology for preventing wasteful power consumption has been disclosed in Japanese Unexamined Patent Publication No. Heisei 10-336749. FIGS. 8A, 8B and 8C are illustration for explaining the technology disclosed in the above-identified publication. Referring to FIG. 8A, a reception signal from an antenna 111 is amplified by an amplifier 112 and is frequency-converted by a local signal in a frequency converter 113. A frequency converted output is converted into a digital signal by an AD converter 114. Furthermore, the digital signal is despreaded with a spread code from a spread code generator 116 by a despreader 115. A despreaded output is subject to signal processing by a signal processor 117 to be supplied to a terminal device (not shown), such as a speaker, personal computer (PC) through a terminal interface portion 118.
As shown in FIG. 8B for example, the spread code generator 116 outputs a spread code from a final stage Se of a shift register 121, and in conjunction therewith, an exclusive OR of the spread code output from the final stage Se and an output of an intermediate shift stage is taken by an exclusive OR circuit 122. The output of the exclusive OR circuit 122 is fed back to the initial stage Si. As initial values, a register value which is not all “0” is input to each shift stage, and then is shifted toward the final stage Se per one stage at every occurrence of a shift clock. Every time of shifting, a value of the shift register 121 is updated.
Only radio channel determined by the spread code is output to the terminal interface portion 118. It is thus required to despread the received signal with the spread code synchronized with the spread code on the transmitter side. The spread code generator 116 is synchronized with the spread code of the reception signal by a not shown synchronization means. Furthermore, synchronization has to be maintained constantly. Upon performing intermittent reception, it should be desirable to stop the spread code generator 116 while receiving operation is no performed, in viewpoint of power consumption. However, in viewpoint of maintaining of synchronization with the spread code on the transmitter side, as shown in FIG. 8(C), a function 123 to read out a register value (condition) of the shift register 121 from time to time is provided to calculate the register value to be updated depending upon a period, in which receiving operation is not performed, on the basis of the read out register by a register value calculating function 124. The register value to be updated which is calculated as set forth above, can be set in the shift register 121 by a register value setting function 125.
Next, operation will be discussed. At first, the register is placed in operating condition and the receiver circuit is also placed in operating condition. Subsequently, upon occurrence of shift clock, the shift register 121 is shifted for one bit. Then, check is made whether a time to turn OFF the receiver circuit is reached or not. If the time is nor reached, the shift register 121 is further shifted for one bit in response to the shift clock. Thereafter, check is again made whether the time to turn OFF the receiver circuit is reached or not. Upon reaching the OFF time, the register value of the shift register 121 is read out by the register value reading out function 123 to feed to the register value calculating function 124.
In the regiser value calculating function 124, the register value (updating condition) upon updating of the condition, which will be obtained when the shift register 121 is shifted during OFF condition of the receiver circuit, is calculated. The updated register value is set in the register 121 by the setting function 125. Subsequently, operation of the register 121 is terminated, and the operation of the receiver circuit is terminated. It should be noted that the register value of the shift register 121 is held in the updated register value set in advance.
In this condition, a time at which the receiver circuit is turned ON next is waited. Upon reaching the ON time, the operation shifts to the first step and the operation set forth above is resumed. Namely, operation can be resumed with the register value the same as that when the operation is continued without interrupting operation of the shift register 121. Accordingly, synchronization with the spread code on the transmitter side can be maintained.
In the technology disclosed in Japanese Unexamined Patent Publication No. Heisei 10-336749, as illustrated in FIG. 8, as set forth above, upon interruption of operation or upon resumption of operation of the shift register 121 forming the code generator 116 for generating code, the updating condition of the register is calculated depending upon the period held inoperative by the register value calculating function 124 to set the result of calculation in the shift register 121. Therefore, a timer for measuring the period held inoperative condition, CPU (arithmetic device) for realizing the register value calculating function 124 are necessary. Then, such timer and CPU cannot interrupt operation even while the register is held inoperative. Therefore, restriction of power consumption cannot be satisfactory.